Abraham Gonzalez

UC Berkeley Ph.D. Candidate

About Me

INTRODUCTIONS

Hello, everyone! My name is Abraham Gonzalez and I am a Electrical Engineering and Computer Science Ph.D. candidate at the University of California at Berkeley in the SLICE lab (formerly the ADEPT lab) under Professor Krste Asanovic. I am a highly motivated individual, passionate on learning more about computer microarchitecture and datacenter computing. I hope to make future computing faster, more efficient, and more available to all. Please read my resume or curriculum vitae for the most up-to-date information on past projects, experiences, and accomplishments of mine.

Documents

Learn More

Curriculum Vitae

Updated Dec. 2024

[Paper PDF]

Resume

Updated Dec. 2024

[Paper PDF]

Work Experience

SKILLS AND LEARNINGS

Computer Architecture Ph.D. Student

SLICE/ADEPT Lab
August 2018 - Now

I am a co-lead on the Chipyard SoC framework and FireSim FPGA-simulation platform. Additionally, I co-lead the Hypercale SoC project focused on HW/SW co-design and accelerator enhancements for warehouse scale computers. In the past, I have worked on the BOOM Out-of-Order Core project. My research interests are in data-analytics acceleration, warehouse-scale computing, high-performance microarchitectures, and making computer architecture tooling easier and more efficient to use. While at Berkeley, I've been a lead organizer for over 10+ tutorials/workshops with over 250+ combined attendees at top architecture conferences such as ISCA, MICRO, ASPLOS, HPCA, and more. Finally, I've published research and tapeouts at top conferences including ISCA, ESSCIRC, and DAC.

  • Chisel/Verilog
  • C++
  • Make
  • Python
  • Bash

System Infrastructure Intern

Google
June 2021 - July 2024

  • Chisel/Verilog
  • SQL
  • Python
  • Bash
  • C/C++

CPU Design Intern

Apple
June 2020 - August 2020

  • C++
  • Make

Scalable CPU Performance Development Group Intern

Intel
May 2018 - August 2018

  • System Verilog
  • Python
  • Make

Microsystems Technology Lab Intern

Massachusetts Institute of Technology
May 2017 - August 2017

  • Tensorflow/Python
  • Machine Learning

Office Shared Graphics Explore Intern

Microsoft
May 2016 - August 2016

  • C++
  • Front-end Development

UIM Driver Intern

Qualcomm
May 2015 - August 2015

  • C++/CLI
  • Smartcard Development

Publications

Accepted and Under Submission

FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs

Joonho Whangbo, Edwin Lim, Chengyi Lux Zhang, Kevin Anderson, Abraham Gonzalez, Raghav Gupta, Nivedha Krishnakumar, Sagar Karandikar, Borivoje Nikolic, Yakun Sophia Shao, Krste Asanovic, "FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs", 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), Buenos Aires, Argentina, June 2024.

[Paper PDF]

Profiling Hyperscale Big Data Processing

Abraham Gonzalez, Aasheesh Kolli, Samira Khan, Sihang Liu, Vidushi Dadu, Sagar Karandikar, Jichuan Chang, Krste Asanovic, Parthasarathy Ranganathan, "Profiling Hyperscale Big Data Processing", 2023 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), Orlando, FL, USA, June 2023.

[Preprint Paper PDF] [Paper PDF]

A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET

Abraham Gonzalez, Jerry Zhao, Ben Korpan, Hasan Genc, Colin Schmidt, John Wright, Ayan Biswas, Alon Amid, Farhana Sheikh, Anton Sorokin, Sirisha Kale, Mani Yalamanchi, Ramya Yarlagadda, Mark Flannigan, Larry Abramowitz, Elad Alon, Yakun Sophia Shao, Krste Asanovic, and Bora Nikolic, "A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET", In proceedings of 2021 IEEE European Solid State Circuits Conference (ESSCIRC 2021), Virtual Event, September 2021.

[Paper PDF]

COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors

Jerry Zhao, Abraham Gonzalez, Alon Amid, Sagar Karandikar, and Krste Asanovic, "COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors", In proceedings of 2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2021), Virtual Event, March 2021.

[Preprint] [Paper PDF]

Chipyard - An Integrated SoC Research and Implementation Environment

Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanovic, and Bora Nikolic, "Invited: Chipyard - An Integrated SoC Research and Implementation Environment", In proceedings of 57th ACM/IEEE Design Automation Conference (DAC 2020), San Francisco, CA, USA, July 2020.

[Preprint] [Paper PDF]

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs

Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanovic, and Bora Nikolic, "Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs", IEEE Micro, vol. 40, no. 4, pp. 10-21, (Special Issue on Agile and Open-Source Hardware), July-August 2020.

[Preprint] [Paper PDF]

SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine

Jerry Zhao, Ben Korpan, Abraham Gonzalez, and Krste Asanovic, "SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine", 4th Workshop on Computer Architecture Research with RISC-V (CARRV 2020), Virtual Event, May 2020.

[Slides] [Paper PDF]

Replicating and Mitigating Spectre Attacks on an Open Source RISC-V Microarchitecture

Abraham Gonzalez, Ben Korpan, Jerry Zhao, Ed Younis, and Krste Asanovic, "Replicating and Mitigating Spectre Attacks on an Open Source RISC-V Microarchitecture", 3rd Workshop on Computer Architecture Research with RISC-V (CARRV 2019), Phoenix, AZ, USA, June 2019.

[Slides] [Paper PDF]

Talks, Tutorials, and Workshops

Public/academic only (excluding invited corporate talks)

Full-day Tutorial on FireSim, Chipyard, Gemmini, and AuRORA at MICRO 2024

Austin, TX, USA, November 2024.

[Event] [Schedule/Slides]

ISCA 2023 Main Conference

"Profiling Hyperscale Data Processing." Orlando, FL, USA, June 2023.

[Event] [Lightning Talk]

Full-day Tutorial on FireSim and Chipyard at ISCA 2023

Orlando, FL, USA, June 2023.

[Event] [Schedule/Slides]

Latch Up 2023

"Chipyard: An Open-Source RISC-V SoC Design Framework." Santa Barbara, CA, USA, April 2023.

[Event] [Video]

First FireSim and Chipyard User and Developer Workshop at ASPLOS 2023

Vancouver, Canada, March 2023.

[Event] [Schedule/Slides]

Full-day Tutorial on FireSim and Chipyard at ASPLOS 2023

Vancouver, Canada, March 2023.

[Event] [Schedule/Slides]

Full-day Tutorial on FireSim and Chipyard at HPCA 2023

Montreal, Canada, February 2023.

[Event] [Schedule/Slides]

Full-day Tutorial on FireSim and Chipyard at MICRO 2022

Chicago, IL, USA, October 2022.

[Event] [Schedule/Slides]

Full-day Tutorial on FireSim and Chipyard at ASPLOS 2022

Lausanne, Switzerland, March 2022.

[Event] [Schedule/Slides]

Full-day Tutorial on FireSim and Chipyard at MICRO 2021

Virtual, October 2021.

[Event] [Schedule/Slides]

ESSCIRC 2021 Main Conference

"A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET." Virtual, September 2021.

[Event]

Full-day Tutorial on FireSim and Chipyard at ISCA 2021

Virtual, June 2021.

[Event] [Link]

Full-day Tutorial on FireSim and Chipyard at MICRO 2019

Colombus, OH, USA, October 2019.

[Event] [Link]

Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019) at ISCA 2019

"Replicating and Mitigating Spectre Attacks on a Open Source RISC-V Microarchitecture." Phoenix, AZ, USA, June 2019.

[Event]

Latch Up 2019

"The Berkeley Out-of-Order Machine. An Open-Source Synthesizable High-Performance RISC-V Processor." Portland, OR, USA, May 2019.

[Event] [Video]