Abraham Gonzalez
Incoming Software Engineer @ Google
Bio
I am an incoming Software Engineer at Google working in the AI and Systems Research group co-led by David Culler and Hank Levy. The best way to reach me is at abe dot gonzalez at berkeley dot edu.
I graduated with a Ph.D. in Electrical Engineering and Computer Sciences at the University of California, Berkeley in Summer 2025 as part of the SLICE lab (formerly the ADEPT lab) under Professor Emeritus and Professor of the Graduate School Krste Asanović and Professor Borivoje Nikolić. As part of my dissertation work, I've worked at Google with Engineering Fellow/VP Parthasarathy Ranganathan and Engineering Director Jichuan Chang. My dissertation focused on hyperscale cloud data center architectures, accelerator scheduling, data analytics, and agile hardware design methodology. I've co-led various widely used open-source projects, including the Chipyard SoC framework, the FireSim FPGA-accelerated simulation platform, and the Berkeley Out-of-Order Machine (BOOM). As of Summer 2025, both Chipyard and FireSim, combined, have been used in over 20 tape-outs and over 150 peer-reviewed publications from over 65 companies and universities. My work has been published in various venues such as ISCA, DAC, IEEE Micro, and ESSCIRC. I've also led over 10 workshops and tutorials with over 200 unique attendees at top conferences such as ISCA, MICRO, ASPLOS, and HPCA.
Prior to Berkeley, I received my B.S. in Electrical and Computer Engineering from the University of Texas at Austin.
Publications
Joonho Whangbo, Edwin Lim, Chengyi Lux Zhang, Kevin Anderson, Abraham Gonzalez, Raghav Gupta, Nivedha Krishnakumar, Sagar Karandikar, Borivoje Nikolić, Yakun Sophia Shao, and Krste Asanović
Abraham Gonzalez, Aasheesh Kolli, Samira Khan, Sihang Liu, Vidushi Dadu, Sagar Karandikar, Jichuan Chang, Krste Asanović, and Parthasarathy Ranganathan
A 16mm² 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET
ESSCIRC '21
Abraham Gonzalez, Jerry Zhao, Ben Korpan, Hasan Genc, Colin Schmidt, John Wright, Ayan Biswas, Alon Amid, Farhana Sheikh, Anton Sorokin, Sirisha Kale, Mani Yalamanchi, Ramya Yarlagadda, Mark Flannigan, Larry Abramowitz, Elad Alon, Yakun Sophia Shao, Krste Asanović, and Borivoje Nikolić
Jerry Zhao, Abraham Gonzalez, Alon Amid, Sagar Karandikar, and Krste Asanović
Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanović, and Borivoje Nikolić
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
IEEE Micro 2020.4
Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanović, and Borivoje Nikolić
Jerry Zhao, Ben Korpan, Abraham Gonzalez, and Krste Asanović
A Chipyard Comparison of NVDLA and Gemmini
UC Berkeley Technical Report '20
Abraham Gonzalez, and Charles Hong
Abraham Gonzalez, Ben Korpan, Jerry Zhao, Ed Younis, and Krste Asanović
Projects
Hyperscale SoC
BIG-DATA PROCESSING • REMOTE PROCEDURE CALLS • MODELING • OPEN-SOURCE
• Co-lead of the project with a focus on co-design of big data processing platforms and RPC accelerator scheduling.
• Characterized three big data processing platforms, Spanner, BigTable, and BigQuery, running live-traffic at Google for the first time and published the work at ISCA '23.
• Open-sourced the HyperRPCBench benchmark suite, a novel representative synthetic RPC suite in collaboration with the Fleetbench benchmarking team.
• Built and correlated Python/C++ models for accelerator runtimes against x86 proof-of-concepts and Chipyard-based RTL simulated with FireSim running HyperRPCBench.
AGILE HARDWARE • SOC DESIGN • OPEN-SOURCE
• Co-lead and core developer of the project with a focus on architecting the main integration, build flow, and repository structure.
• Added support for multiple IPs including BOOM, Rocket Chip blocks (SiFive blocks), Ariane (CVA6), NVDLA, and more.
• Integrated the initial tape-out bring-up tether widget, FPGA bring-up flow, and software utilities.
• Added the initial CI/CD flow including torture/fuzz and distributed testing.
• As of Summer 2025, the project has been used in over 20 tape-outs at multiple academic institutions (such as Stanford and Technical University of Dresden). Additionally, it has been cited by over 350 papers and used for a variety of works spanning computer architecture, artifical intelligence (AI), programming languages, systems, and more with over 650 unique forks and 1.8K stars on GitHub.
HARDWARE SIMULATION • FPGA • OPEN-SOURCE
• Co-lead and core developer of the project with a focus on adding local FPGA support, re-architecting the cluster manager, and developer tooling.
• Integrated Dromajo co-simulation to enable bug discovery billions of cycles into simulation.
• Re-architected the command-line interface and Python machine manager to support configurable custom clusters, enabling larger simulations through local FPGA support with U250/U280/U200 Xilinx UltraScale+ FPGAs and the Xilinx Vitis Unified Software Platform.
• Expanded the initial CI/CD flow to include FPGA bitstream builds and simulations across local and cloud FPGAs.
• Used as a standard host platform for DARPA and IARPA programs, including in DARPA's first ever bug bounty program (FETT) to host novel security-augmented hardware designs on the internet for attack by 100s of white-hat hackers globally.
• As of Summer 2025, the project has been used (not only cited) in over 60 peer-reviewed publications from first authors at over 25 companies and academic institutions in addition to being used in the development of commercial chips. Additionally, it has over 200 unique forks and 900 stars on GitHub.
BEAGLE: Heterogeneous Multi-Core Multi-Accelerator Tape-out
MULTI-ACCELERATOR • MACHINE LEARNING • VECTOR • OPEN-SOURCE
• Led tape-out of the first Chipyard test chip, a 106.1 GOPS/W heterogeneous multi-core multi-accelerator test chip made in Intel 22FFL and published at ESSCIRC '21.
• Coordinated interaction between UC Berkeley and Intel during physical design process.
• Streamlined Chipyard vendor IP integration and custom boot flow.
• Led bring-up including open-sourcing newly created FPGA-based bring-up collateral.
• Led pre-silicon testing with large-scale FireSim simulations and automated Chipyard regressions.
• SoC Components: In-order Rocket core with a Gemmini systolic array accelerator, out-of-order BOOM core with a Hwacha vector accelerator and runtime configurable non-speculative mode, shared L2, independent clock domains, and multiple IOs (GPIO, SPI, I2C, UART, SerDes).
HIGH-PERFORMANCE • GENERAL PURPOSE • OPEN-SOURCE
• Developer of the first open-source synthesizable Linux-booting RV64GC RISC-V out-of-order core.
• Added the initial CI/CD flow including torture/fuzz and distributed testing.
• Modified the RTL to support instantiation with other core IPs in additional to various quality-of-life improvements.
• Open-sourced and replicated Spectre speculative attacks on the core.